🚀 Accelerating System Design in Advanced Semiconductors!

[Semih Asil]

🤝 Synopsys and TSMC's Major Collaboration​

Synopsys and TSMC are joining forces to accelerate the design of high-performance computing components for advanced semiconductors. This collaboration aims to streamline the design, verification, and packaging of complex multi-die systems and high-performance computing (HPC) hardware by integrating automated EDA workflows and unified multi-physics verification processes.

🧠 AI-Powered Engineering​

Modern hardware development requires the integration of diverse logic, memory, and optical chipsets into a single package. These heterogeneous multi-die architectures present significant challenges such as power integrity, thermal management, and spatial layout planning that exceed traditional engineering capabilities. Synopsys and TSMC are addressing these challenges by directly combining Synopsys' computational EDA software with TSMC's proprietary silicon process nodes and 3DFabric packaging methodologies.

This deep integration allows hardware engineers to accurately verify physical layout, power delivery, and thermal tolerances before committing to physical silicon fabrication. Michael Buehler-Garcia, Senior Vice President at Synopsys, states that these joint innovations address the continuum of silicon-to-system co-design capabilities essential for the development of high-performance computing systems.

✅ Certified EDA Workflows and AI Automation​

A key outcome of the collaboration is the certification of Synopsys EDA flows for TSMC's A14 process technology. This certification provides hardware developers with a verified digital and analog implementation framework, ensuring that design convergence meets the stringent physical parameters of the A14 node. In analog design, the partnership enables device routing on A14, automating complex placement and routing tasks to improve layout efficiency.

To address the complexity of heterogeneous packaging, the partners have implemented agent-based AI capabilities within the Synopsys 3DIC Compiler platform. This specialized workflow uses AI to automate the co-optimization of chipset layout planning, thereby accelerating the spatial arrangement of multiple dies while adhering to the physical constraints of TSMC 3DFabric technologies. Furthermore, for integrated voltage regulators (IVRs), which are critical for stabilizing power delivery in multi-die arrays, the 3DIC platform now allows engineers to co-design and simulate IVR structures directly on TSMC CoWoS (Chip-on-Wafer-on-Substrate) packaging.

💡 Optical Interconnects and Physical IP​

As data bandwidth requirements increase, the collaboration also targets co-packaged optics (CPO). Synopsys and TSMC have developed an integrated photonic and electronic co-design flow for TSMC's COUPE technology. This workflow combines 3DIC physical implementation with multi-physics analysis, allowing engineers to verify advanced optical interconnect architectures without using separate software toolchains.

At the hardware level, Synopsys continues to expand its portfolio of silicon-proven physical intellectual property (IP) optimized for TSMC's 3nm and 2nm nodes. The collaboration recently achieved physical tape-out milestones on the TSMC N2P process for critical connectivity and memory interfaces, including PCIe 7.0, HBM4, and 224G Ethernet PHY. For multi-die connectivity, Synopsys validated its UCIe-A 32G/40G IP on a TSMC N3P test chip utilizing a CoWoS-S interposer, confirming the stability of high-speed die-to-die communication required for scaled HPC workloads.